Fix T61801: Wireframes on curves not working
This commit is contained in:
parent
a7acd4690c
commit
753e73009f
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@ -81,12 +81,12 @@ struct GPUBatch **DRW_metaball_batch_cache_get_surface_shaded(
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struct GPUBatch *DRW_metaball_batch_cache_get_wireframes_face(struct Object *ob);
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/* DispList */
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void DRW_displist_vertbuf_create_pos_and_nor(struct ListBase *lb, struct GPUVertBuf *vbo);
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void DRW_displist_vertbuf_create_pos_and_nor_and_uv_tess(
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void DRW_displist_vertbuf_create_pos_and_nor_and_wiredata(struct ListBase *lb, struct GPUVertBuf *vbo);
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void DRW_displist_vertbuf_create_loop_pos_and_nor_and_uv(
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struct ListBase *lb, struct GPUVertBuf *vbo_pos_nor, struct GPUVertBuf *vbo_uv);
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void DRW_displist_vertbuf_create_wireframe_data_tess(struct ListBase *lb, struct GPUVertBuf *vbo);
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void DRW_displist_indexbuf_create_triangles_in_order(struct ListBase *lb, struct GPUIndexBuf *vbo);
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void DRW_displist_indexbuf_create_triangles_tess_split_by_material(
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void DRW_displist_indexbuf_create_lines_in_order(struct ListBase *lb, struct GPUIndexBuf *ibo);
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void DRW_displist_indexbuf_create_triangles_in_order(struct ListBase *lb, struct GPUIndexBuf *ibo);
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void DRW_displist_indexbuf_create_triangles_loop_split_by_material(
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struct ListBase *lb, struct GPUIndexBuf **ibo_mat, uint mat_len);
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/* Lattice */
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@ -347,15 +347,11 @@ typedef struct CurveBatchCache {
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struct {
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GPUVertBuf *pos_nor;
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GPUVertBuf *curves_pos;
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GPUVertBuf *loop_pos_nor;
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GPUVertBuf *loop_uv;
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} ordered;
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struct {
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GPUVertBuf *pos_nor;
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GPUVertBuf *uv;
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GPUVertBuf *wireframe_data;
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} tess;
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struct {
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/* Curve points. Aligned with ordered.pos_nor */
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GPUVertBuf *curves_nor;
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@ -367,6 +363,7 @@ typedef struct CurveBatchCache {
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struct {
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GPUIndexBuf *surfaces_tris;
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GPUIndexBuf *surfaces_lines;
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GPUIndexBuf *curves_lines;
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/* Edit mode */
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GPUIndexBuf *edit_verts_points; /* Only control points. Not handles. */
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@ -375,14 +372,13 @@ typedef struct CurveBatchCache {
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struct {
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GPUBatch *surfaces;
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GPUBatch *surfaces_edges;
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GPUBatch *curves;
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/* control handles and vertices */
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GPUBatch *edit_edges;
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GPUBatch *edit_verts;
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GPUBatch *edit_handles_verts;
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GPUBatch *edit_normals;
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/* Triangles for object mode wireframe. */
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GPUBatch *wire_triangles;
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} batch;
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GPUIndexBuf **surf_per_mat_tris;
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@ -506,10 +502,6 @@ static void curve_batch_cache_clear(Curve *cu)
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GPUVertBuf **vbo = (GPUVertBuf **)&cache->ordered;
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GPU_VERTBUF_DISCARD_SAFE(vbo[i]);
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}
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for (int i = 0; i < sizeof(cache->tess) / sizeof(void *); ++i) {
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GPUVertBuf **vbo = (GPUVertBuf **)&cache->tess;
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GPU_VERTBUF_DISCARD_SAFE(vbo[i]);
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}
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for (int i = 0; i < sizeof(cache->edit) / sizeof(void *); ++i) {
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GPUVertBuf **vbo = (GPUVertBuf **)&cache->edit;
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GPU_VERTBUF_DISCARD_SAFE(vbo[i]);
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@ -884,7 +876,7 @@ GPUBatch **DRW_curve_batch_cache_get_surface_shaded(
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GPUBatch *DRW_curve_batch_cache_get_wireframes_face(Curve *cu)
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{
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CurveBatchCache *cache = curve_batch_cache_get(cu);
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return DRW_batch_request(&cache->batch.wire_triangles);
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return DRW_batch_request(&cache->batch.surfaces_edges);
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}
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/** \} */
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@ -920,14 +912,14 @@ void DRW_curve_batch_cache_create_requested(Object *ob)
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DRW_ibo_request(cache->batch.surfaces, &cache->ibo.surfaces_tris);
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DRW_vbo_request(cache->batch.surfaces, &cache->ordered.pos_nor);
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}
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if (DRW_batch_requested(cache->batch.surfaces_edges, GPU_PRIM_LINES)) {
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DRW_ibo_request(cache->batch.surfaces_edges, &cache->ibo.surfaces_lines);
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DRW_vbo_request(cache->batch.surfaces_edges, &cache->ordered.pos_nor);
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}
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if (DRW_batch_requested(cache->batch.curves, GPU_PRIM_LINE_STRIP)) {
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DRW_ibo_request(cache->batch.curves, &cache->ibo.curves_lines);
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DRW_vbo_request(cache->batch.curves, &cache->ordered.curves_pos);
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}
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if (DRW_batch_requested(cache->batch.wire_triangles, GPU_PRIM_TRIS)) {
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DRW_vbo_request(cache->batch.wire_triangles, &cache->tess.pos_nor);
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DRW_vbo_request(cache->batch.wire_triangles, &cache->tess.wireframe_data);
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}
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/* Edit mode */
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if (DRW_batch_requested(cache->batch.edit_edges, GPU_PRIM_LINES)) {
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@ -953,9 +945,9 @@ void DRW_curve_batch_cache_create_requested(Object *ob)
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DRW_ibo_request(cache->surf_per_mat[i], &cache->surf_per_mat_tris[i]);
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}
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if (cache->cd_used & CD_MLOOPUV) {
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DRW_vbo_request(cache->surf_per_mat[i], &cache->tess.uv);
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DRW_vbo_request(cache->surf_per_mat[i], &cache->ordered.loop_uv);
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}
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DRW_vbo_request(cache->surf_per_mat[i], &cache->tess.pos_nor);
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DRW_vbo_request(cache->surf_per_mat[i], &cache->ordered.loop_pos_nor);
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}
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}
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@ -963,10 +955,10 @@ void DRW_curve_batch_cache_create_requested(Object *ob)
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int mr_flag = 0;
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->ordered.pos_nor, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->ordered.curves_pos, CU_DATATYPE_WIRE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->tess.pos_nor, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->tess.uv, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->tess.wireframe_data, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->ordered.loop_pos_nor, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->ordered.loop_uv, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_IBO_REQUEST(mr_flag, cache->ibo.surfaces_tris, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_IBO_REQUEST(mr_flag, cache->ibo.surfaces_lines, CU_DATATYPE_SURFACE);
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DRW_ADD_FLAG_FROM_IBO_REQUEST(mr_flag, cache->ibo.curves_lines, CU_DATATYPE_WIRE);
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DRW_ADD_FLAG_FROM_VBO_REQUEST(mr_flag, cache->edit.pos, CU_DATATYPE_OVERLAY);
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@ -987,23 +979,20 @@ void DRW_curve_batch_cache_create_requested(Object *ob)
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/* Generate VBOs */
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if (DRW_vbo_requested(cache->ordered.pos_nor)) {
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DRW_displist_vertbuf_create_pos_and_nor(lb, cache->ordered.pos_nor);
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DRW_displist_vertbuf_create_pos_and_nor_and_wiredata(lb, cache->ordered.pos_nor);
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}
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if (DRW_vbo_requested(cache->ordered.curves_pos)) {
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curve_create_curves_pos(rdata, cache->ordered.curves_pos);
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}
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if (DRW_vbo_requested(cache->tess.pos_nor) ||
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DRW_vbo_requested(cache->tess.uv))
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if (DRW_vbo_requested(cache->ordered.loop_pos_nor) ||
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DRW_vbo_requested(cache->ordered.loop_uv))
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{
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DRW_displist_vertbuf_create_pos_and_nor_and_uv_tess(lb, cache->tess.pos_nor, cache->tess.uv);
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}
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if (DRW_vbo_requested(cache->tess.wireframe_data)) {
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DRW_displist_vertbuf_create_wireframe_data_tess(lb, cache->tess.wireframe_data);
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DRW_displist_vertbuf_create_loop_pos_and_nor_and_uv(lb, cache->ordered.loop_pos_nor, cache->ordered.loop_uv);
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}
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if (DRW_ibo_requested(cache->surf_per_mat_tris[0])) {
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DRW_displist_indexbuf_create_triangles_tess_split_by_material(lb, cache->surf_per_mat_tris, cache->mat_len);
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DRW_displist_indexbuf_create_triangles_loop_split_by_material(lb, cache->surf_per_mat_tris, cache->mat_len);
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}
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if (DRW_ibo_requested(cache->ibo.curves_lines)) {
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@ -1012,6 +1001,9 @@ void DRW_curve_batch_cache_create_requested(Object *ob)
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if (DRW_ibo_requested(cache->ibo.surfaces_tris)) {
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DRW_displist_indexbuf_create_triangles_in_order(lb, cache->ibo.surfaces_tris);
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}
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if (DRW_ibo_requested(cache->ibo.surfaces_lines)) {
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DRW_displist_indexbuf_create_lines_in_order(lb, cache->ibo.surfaces_lines);
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}
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if (DRW_vbo_requested(cache->edit.pos) ||
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DRW_vbo_requested(cache->edit.data) ||
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@ -165,14 +165,15 @@ static int displist_indexbufbuilder_tess_set(
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return v_idx;
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}
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void DRW_displist_vertbuf_create_pos_and_nor(ListBase *lb, GPUVertBuf *vbo)
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void DRW_displist_vertbuf_create_pos_and_nor_and_wiredata(ListBase *lb, GPUVertBuf *vbo)
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{
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static GPUVertFormat format = { 0 };
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static struct { uint pos, nor; } attr_id;
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static struct { uint pos, nor, wd; } attr_id;
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if (format.attr_len == 0) {
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/* initialize vertex format */
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attr_id.pos = GPU_vertformat_attr_add(&format, "pos", GPU_COMP_F32, 3, GPU_FETCH_FLOAT);
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attr_id.nor = GPU_vertformat_attr_add(&format, "nor", GPU_COMP_I16, 4, GPU_FETCH_INT_TO_FLOAT_UNIT);
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attr_id.wd = GPU_vertformat_attr_add(&format, "wd", GPU_COMP_U8, 1, GPU_FETCH_INT_TO_FLOAT_UNIT);
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}
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GPU_vertbuf_init_with_format(vbo, &format);
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@ -188,6 +189,8 @@ void DRW_displist_vertbuf_create_pos_and_nor(ListBase *lb, GPUVertBuf *vbo)
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const float *fp_no = dl->nors;
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const int vbo_end = vbo_len_used + dl_vert_len(dl);
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while (vbo_len_used < vbo_end) {
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uchar sharpness = 0xFF;
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GPU_vertbuf_attr_set(vbo, attr_id.wd, vbo_len_used, &sharpness);
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GPU_vertbuf_attr_set(vbo, attr_id.pos, vbo_len_used, fp_co);
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if (fp_no) {
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static short short_no[4];
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@ -224,7 +227,7 @@ void DRW_displist_indexbuf_create_triangles_in_order(ListBase *lb, GPUIndexBuf *
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GPU_indexbuf_build_in_place(&elb, ibo);
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}
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void DRW_displist_indexbuf_create_triangles_tess_split_by_material(
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void DRW_displist_indexbuf_create_triangles_loop_split_by_material(
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ListBase *lb,
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GPUIndexBuf **ibo_mats, uint mat_len)
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{
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@ -252,65 +255,39 @@ void DRW_displist_indexbuf_create_triangles_tess_split_by_material(
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}
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}
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typedef struct DRWDisplistWireThunk {
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uint wd_id, ofs;
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const DispList *dl;
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GPUVertBuf *vbo;
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} DRWDisplistWireThunk;
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static void set_overlay_wires_tri_indices(void *thunk, uint v1, uint v2, uint v3)
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{
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DRWDisplistWireThunk *dwt = (DRWDisplistWireThunk *)thunk;
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uint indices[3] = {v1, v2, v3};
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for (int i = 0; i < 3; ++i) {
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/* TODO: Compute sharpness. For now, only tag real egdes. */
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uchar sharpness = 0xFF;
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GPU_vertbuf_attr_set(dwt->vbo, dwt->wd_id, indices[i], &sharpness);
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}
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GPUIndexBufBuilder *eld = (GPUIndexBufBuilder *)thunk;
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GPU_indexbuf_add_line_verts(eld, v1, v2);
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GPU_indexbuf_add_line_verts(eld, v2, v3);
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GPU_indexbuf_add_line_verts(eld, v3, v1);
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}
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static void set_overlay_wires_quad_tri_indices(void *thunk, uint v1, uint v2, uint v3)
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{
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DRWDisplistWireThunk *dwt = (DRWDisplistWireThunk *)thunk;
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uint indices[3] = {v1, v2, v3};
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for (int i = 0; i < 3; ++i) {
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/* TODO: Compute sharpness. For now, only tag real egdes. */
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uchar sharpness = (i == 0) ? 0x00 : 0xFF;
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GPU_vertbuf_attr_set(dwt->vbo, dwt->wd_id, indices[i], &sharpness);
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}
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GPUIndexBufBuilder *eld = (GPUIndexBufBuilder *)thunk;
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GPU_indexbuf_add_line_verts(eld, v1, v3);
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GPU_indexbuf_add_line_verts(eld, v3, v2);
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}
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/* TODO reuse the position and normals from other tesselation vertbuf. */
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void DRW_displist_vertbuf_create_wireframe_data_tess(ListBase *lb, GPUVertBuf *vbo)
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void DRW_displist_indexbuf_create_lines_in_order(ListBase *lb, GPUIndexBuf *ibo)
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{
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static DRWDisplistWireThunk thunk;
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static GPUVertFormat format = {0};
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if (format.attr_len == 0) {
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thunk.wd_id = GPU_vertformat_attr_add(&format, "wd", GPU_COMP_U8, 1, GPU_FETCH_INT_TO_FLOAT_UNIT);
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GPU_vertformat_triple_load(&format);
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}
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const int tri_len = curve_render_surface_tri_len_get(lb);
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const int vert_len = curve_render_surface_vert_len_get(lb);
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GPU_vertbuf_init_with_format(vbo, &format);
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thunk.vbo = vbo;
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GPUIndexBufBuilder elb;
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GPU_indexbuf_init(&elb, GPU_PRIM_LINES, tri_len * 3, vert_len);
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int vert_len = curve_render_surface_tri_len_get(lb) * 3;
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GPU_vertbuf_data_alloc(thunk.vbo, vert_len);
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thunk.ofs = 0;
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int ofs = 0;
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for (const DispList *dl = lb->first; dl; dl = dl->next) {
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thunk.dl = dl;
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/* TODO consider non-manifold edges correctly. */
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thunk.ofs = displist_indexbufbuilder_tess_set(
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set_overlay_wires_tri_indices,
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set_overlay_wires_quad_tri_indices,
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&thunk, dl, thunk.ofs);
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displist_indexbufbuilder_set(
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(SetTriIndicesFn *)set_overlay_wires_tri_indices,
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(SetTriIndicesFn *)set_overlay_wires_quad_tri_indices,
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&elb, dl, ofs);
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ofs += dl_vert_len(dl);
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}
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if (thunk.ofs < vert_len) {
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GPU_vertbuf_data_resize(thunk.vbo, thunk.ofs);
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}
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GPU_indexbuf_build_in_place(&elb, ibo);
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}
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static void surf_uv_quad(const DispList *dl, const uint quad[4], float r_uv[4][2])
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@ -364,7 +341,7 @@ static void displist_vertbuf_attr_set_tri_pos_nor_uv(
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}
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}
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void DRW_displist_vertbuf_create_pos_and_nor_and_uv_tess(
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void DRW_displist_vertbuf_create_loop_pos_and_nor_and_uv(
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ListBase *lb,
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GPUVertBuf *vbo_pos_nor, GPUVertBuf *vbo_uv)
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{
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@ -139,7 +139,7 @@ static GPUVertBuf *mball_batch_cache_get_pos_and_normals(Object *ob, MetaBallBat
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if (cache->pos_nor_in_order == NULL) {
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ListBase *lb = &ob->runtime.curve_cache->disp;
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cache->pos_nor_in_order = MEM_callocN(sizeof(GPUVertBuf), __func__);
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DRW_displist_vertbuf_create_pos_and_nor(lb, cache->pos_nor_in_order);
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DRW_displist_vertbuf_create_pos_and_nor_and_wiredata(lb, cache->pos_nor_in_order);
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}
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return cache->pos_nor_in_order;
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}
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@ -203,13 +203,15 @@ GPUBatch *DRW_metaball_batch_cache_get_wireframes_face(Object *ob)
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ListBase *lb = &ob->runtime.curve_cache->disp;
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GPUVertBuf *vbo_pos_nor = MEM_callocN(sizeof(GPUVertBuf), __func__);
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GPUVertBuf *vbo_wireframe_data = MEM_callocN(sizeof(GPUVertBuf), __func__);
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DRW_displist_vertbuf_create_pos_and_nor_and_wiredata(lb, vbo_pos_nor);
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DRW_displist_vertbuf_create_pos_and_nor_and_uv_tess(lb, vbo_pos_nor, NULL);
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DRW_displist_vertbuf_create_wireframe_data_tess(lb, vbo_wireframe_data);
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GPUIndexBuf *ibo = MEM_callocN(sizeof(GPUIndexBuf), __func__);
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DRW_displist_indexbuf_create_lines_in_order(lb, ibo);
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cache->face_wire.batch = GPU_batch_create_ex(GPU_PRIM_TRIS, vbo_pos_nor, NULL, GPU_BATCH_OWNS_VBO);
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GPU_batch_vertbuf_add_ex(cache->face_wire.batch, vbo_wireframe_data, true);
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cache->face_wire.batch = GPU_batch_create_ex(GPU_PRIM_LINES,
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vbo_pos_nor,
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ibo,
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GPU_BATCH_OWNS_VBO | GPU_BATCH_OWNS_INDEX);
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}
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return cache->face_wire.batch;
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