Overview

AMD Radeon RDNA2 architecture adds support for hardware accelerated ray intersection and BVH traversal. This is exposed in OpenCL via a “hardware intrinsic”. We will use this to modify the existing OpenCL path in Cycles to use a separate hardware accelerated code path when device support is present.

From a user point of view, they continue using the OpenCL version of cycles, and we automatically enable hw raytracing if available.

Design
Enablement:

• A flag in the make file

WITH_CYCLES_DEVICE_AMD_HW

• If the cmake flag is set, device capabilities are assessed for HW raytracing and if available, HW RT is enabled

Host side, BVH

• Addition of a new BVH layout mask (bvh_amd)
• Addition of a new bvh class to generate hw compatible bvh and pack instances accordingly
  • QBVH based with top level bounding boxes, up to depth 5, with full precision and the rest with half precision

Host side, Device

more details to come...

Detecting device compatibility

When AMD HW raytracing flag is set, the hardware ray tracing capability is queried in the OpenCLDevice constructor. The result of the query is checked when assigning the BVH layout and when kernels are compiled. The BVH layout routes the BVH creation to BVHAMD class and later in the BVH building, methods of this class are used to pack nodes and generate the hardware compatible BVH. The compiler options routes the intersection calls to the appropriate BVH function where AMD hardware supported intersection functionality is used.

(Patch to be public soon)